A Novel High Speed Convolution and De-convolution Algorithm Implementation Based On Ancient Indian Vedic Mathematics

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0514-0517

Attractive and Repulsive Particle Swarm Optimization Algorithm Based Wirelength Minimization in FPGA Placement

Authors:B. PREMALATHA, DR. S. UMAMAHESWARI

0518-0522

A High Speed Modified Design of Effective Sign Detection Algorithm for Residue Number System

Authors:RANA SIDDIQUA, M. DEVADAS

0523-0526

Simulation of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications

Authors:THAKUR NIROSHA SINGH, M. A. HIMAYATH SHAMSHI

0527-0533

VLSI Design of a CORDIC Algorithm Based FFT Processor

Authors:S. PRAVEEN KUMAR, M. PAVITHRA

0534-0537

Design and Implementation of High Performance 64-Bit Mac Unit for Digital Filters

Authors:SK. MADHAR, SWETCHA, A. VENKATESHWARLU

0538-0542

Improve the Efficiency of FPGAs Based On Multi-operand Redundant Adders

Authors:CH. NARESH, SWETCHA, A. VENKATESHWARLU

0543-0547

Area Delay and Power Efficient Carry Select Adder

Authors:B. LAKSHMAN SAI AVINASH, T. CHAKRAPANI

0548-0552

Implementation of Intelligence Traffic Light Controller Based on FPGA with VHDL

Authors:SK. SHAKEEL, G. DHANALAKSHMI, A. VENKATESHWARLU

0553-0558